High-end microcontroller applications for automotive products need a big number of electrically erasable programmable read only memory (EEPROM) which is usually emulated by on-chip Flash. While both EEPROM and Flash memory allow data to remain stored even when the memory is not powered and therefore both belong to the class of non-volatile memory, EEPROM and Flash memory differ from each other in the way they allow data which is stored in the memory to be erased. Generally, EEPROM can be erased with a finer granularity than Flash memory.
Flash memory is structured as a collection of blocks of memory cells. In operation of the memory, a block has to be erased before new data can be written to this block. There are two types of Flash memory: NOR memories and NAND memories. In the NOR type, memory cells can generally be programmed and read one byte or one word at a time. In the NAND type, however, each block is divided into a certain number of pages, with each page containing a certain number of memory cells. Programming and reading of NAND Flash can only be done in pages, not in bytes or words. NOR type arrays offer fast random read access whereas NAND type arrays have relatively slow random access. The finer program granularity and the faster read access time are reasons why usually NOR type Flash or architectures with similar characteristics are chosen for the emulation of an EEPROM.
Typical erase or block sizes of Flash memories used for EEPROM emulation are: minimum one word line (around 256 Bytes to 1024 Bytes); often there are bigger sizes around 4 KiloBytes (KB) to 16 KB or even more (e.g. 64 KB). The block size depends on the architecture which is designed in a way to support the EEPROM emulation requirements of the end user.
Therefore, since Flash memory cannot be erased with fine EEPROM-like granularity (e.g. bit-wise or 1 Byte) it is necessary to emulate an EEPROM function by writing updates at free places of the Flash memory and keep the logical address information within the data written, since there is no 1:1 correlation of logical and physical address anymore.
If a data word is to be updated, the new version will be programmed at a free place in a sub-sector. The data words contain address and history so that always the most recent data word can be identified. If the sub-sector is full, only the most recent versions of the data words will be copied into the next sub-sector; then the previous sub-sector is erased to offer free place for the next EEPROM updates. This emulation scheme needs more physical Flash cells because the old versions of data are not immediately erased. Therefore, the size of a Flash memory employed for emulating an EEPROM has to be larger than the size of this EEPROM.
Usually, the Flash memory size (flash_size) required for emulating an EEPROM of a given size (EEPROM_size) is expressed as a multiple of the size of the EEPROM (flash_size=factor×EEPROM_size). Conventional emulating schemes typically result in factors between 4.5 and 6. Therefore, for emulating an EEPROM of 128 KB, a Flash memory of up to 768 KB is required. A bigger Flash memory, however, requires more physical space than a smaller Flash memory and results in higher costs of the system used for emulating the EEPROM. Therefore, at present, it is difficult to keep a system for emulating an EEPROM by Flash memory small and cheap.
For these or other reasons there is a need for improved systems and methods for emulating an EEPROM by Flash memory.